MagicEngine

[Tomaitheous]

Hey Charles,

I did a test timed loop with ST1/ST2 and it appears to be 5 cycles regardless of the speed set by the VCE and not 4 like I was hoping. I was thinking the extra cycle came into play because the CPU was sending data faster than the 5.37mhz mode VDC, but setting the VDC to 7.16mhz didn't remove the 1 cycle delay - though I haven't tested it with TIA instruction.

I'm testing some CPU instructions and they're turning out to be slower than a normal 65c02 reference (WDC core) timed cycles too. Weird.

Any word on your tests you mentioned?

-Rich


Edit: It looks like any opcodes with the operand(s) requiring an address bus read/write(ZP, absolute, short signed absolute) have an additional cycle added to the count. Opcodes with implied to immediate operand match up to the WDC/Rockwell 65c02 core rating system. I still need to do more tests, but I think the extra clock cycle is from the MPR address translation logic.
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[shaneandriu]

When a logic SET prefix, the operation would take place in the accumulator has instead turned into a memorial to zero page indexed by the register X. The accumulator is not affected in the corresponding instructions way.The formally documented? Or is it the same in the case of Hitachi 6309 in native mode is not documented years later.
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