PC Engine Hardware : VDC

I/O ports :

The VDC (Video Display Controller) can be accessed through two 16-bit I/O ports in the hardware page (bank $FF) :

Status/Index Register
$0000 R/ bit 0 : Sprite collision flag, set when sprite #0 is in collision with any other sprites.
bit 1 : Sprite overflow flag, set whenever the sprite data could not be fetched, usualy when there are more than 16 sprites on a scanline.
bit 2 : Scanline interrupt flag.
bit 3 : VRAM to SATB end of transfer flag.
bit 4 : VRAM DMA end of transfer flag, set to indicate the end of a VRAM to VRAM DMA transfer.
bit 5 : Vertical blanking flag.
$0000  /W bit 0-4 : VDC register Index.
Select which VDC register (0-19) will be accessible at I/O port $0002

Data Register
$0002 R/W bit 0-15 : Data to be read/written to a VDC register.

VDC registers :

The VDC has a total of 20 16-bit registers.

Note : Two of these registers are reserved and should not be accessed : registers $03 and $04.

Memory Address Write Register
$00  /W bit 0-15 : VRAM write pointer,
set this register to the VRAM location you want to change and write the new data in register $02. (auto-incremented after a write of the high byte of register $02).

Memory Address Read Register
$01  /W bit 0-15 : VRAM read pointer,
set this register to the VRAM location you want to read and get the data from register $02. (auto-incremented after a read of the high byte of register $02).

VRAM Data Register
$02 R/ bit 0-15 : VRAM read latch,
contains the data of the VRAM location pointed to by register $01.
$02  /W bit 0-15 : VRAM write latch,
data written into this register will be copied to the VRAM location pointed to by register $00.

Control Register
$05  /W bit 0 : Sprite collision interrupt enable flag
(between sprite #0 and any other sprite).
bit 1 : Sprite overflow interrupt enable flag
(more than 16 sprites on a scanline).
bit 2 : Scanline interrupt enable flag.
bit 3 : Vertical blanking interrupt enable flag.
  (1 = interrupt on, 0 = off)
bit 4-5 : Reserved - always set to 0.
bit 6 : Sprites enable flag (1 = on).
bit 7 : Background enable flag (1 = on).
bit 8-10 : Reserved - always set to 0.
bit 11-12 : Read/write address auto-increment :

  00 = +1
  01 = +32
  10 = +64
  11 = +128

Set the auto-increment value for memory address register $00 and $01.

Raster Counter Register
$06  /W bit 0-9 : Scanline on which an interrupt should be raised (the first scanline of the screen is scanline number 64).

Background X Scroll Register
$07  /W bit 0-9 : Horizontal screen position in the virtual BG map. Each time the VDC renders a scanline it gets the screen starting X position from this register (some pretty nice effects can be done by just changing this register every scanline: distortion, sine scroll, etc...).

Background Y Scroll Register
$08  /W bit 0-8 : Vertical screen position in the virtual BG map. Same principle as register $07 but for the vertical position.

Memory Access Width Register
$09  /W bit 0-3 : Reserverd - always set to 0.
bit 4-6 : BG map virutal size :

  000 -   32 x 32
  001 -   64 x 32
  010 - 128 x 32
  011 - 128 x 32
  100 -   32 x 64
  101 -   64 x 64
  110 - 128 x 64
  111 - 128 x 64
bit 7 : Reserverd - always set to 0.

VDC display registers :

Registers $0A to $0E hold values used to build the display. They contain settings for the vertical and horizontal synchro signals, as well as for the screen geometry. Playing with these registers could damage your TV or your monitor if you enter incorrect values. They are documented here for completeness, but be careful if you want to play with them... Reference values for setting up a 256x240 screen are given for each register.

Horizontal Synchro Register [ref. $0202]
$0A  /W bit 0-4 : Horizontal synchro width.
bit 8-14 : Horizontal display start position.

Horizontal Display Register [ref. $031F]
$0B  /W bit 0-6 : Horizontal display width.
bit 8-14 : Horizontal display end position.

Vertical Synchro Register [ref. $0F02]
$0C  /W bit 0-4 : Vertical synchro width.
bit 8-15 : Vertical display start position.

Vertical Display Register [ref. $00EF]
$0D  /W bit 0-8 : Vertical display width.

Vertical Display End Position Register [ref. $0003]
$0E  /W bit 0-7 : Vertical display end position.

VDC DMA registers :

The VDC has two DMA channels, one used to do VRAM to VRAM transfers, and another dedicated to VRAM to SATB transfers. The SATB is the Sprite Attribute Table Block, it contains all the sprite informations. It's located inside the VDC and can not be accessed directly, the only way to change sprite attributes is through a local SATB in VRAM that is transfered to the VDC internal SATB each frame using the VRAM to SATB DMA channel.

DMA Control Register
$0F  /W bit 0 : VRAM to SATB end of transfer interrupt enable flag (1 = on).
bit 1 : VRAM to VRAM end of transfer interrupt enable flag (1 = on).
bit 2 : Source address direction, '1' to decrement and '0' to increment.
bit 3 : Destination address direction, '1' to decrement and '0' to increment.
bit 4 : SATB DMA auto-transfer enable flag (1 = on).

DMA Source Address Regiser
$10  /W bit 0-15 : Source address for VRAM to VRAM DMA transfer.

DMA Destination Address Regiser
$11  /W bit 0-15 : Destination address for VRAM to VRAM DMA transfer.

DMA Transfer Length Register
$12  /W bit 0-15 : Length in words of the VRAM to VRAM DMA transfer. Writing to the high byte of this register will auto-start the DMA transfer.

VRAM-SATB Source Address Register
$13  /W bit 0-15 : VRAM source address for the SATB DMA transfer. Writing to this register will auto-start the SATB DMA at the next vertical sync, even if bit 4 in register $0F is not set, however, the transfer will be repeated every vertical sync only if this bit is set.